Current Issue : July - September Volume : 2012 Issue Number : 3 Articles : 5 Articles
Functional programming languages offer a high degree of abstractions and clean semantics, which are desirable for hardware\r\ndescriptions. This short historical survey is about functional languages specifically created for hardware design and verification. It\r\nalso includes those hardware languages or formalisms which are strongly influenced by functional programming style....
Scaling CMOS process technology continues to enable increased levels of system integration, leading to on-chip communication\r\ndemands beyond what traditional digital signaling techniques can efficiently provide with sufficient reliability. In this paper we\r\nsurvey the state of the art of on-chip interconnect techniques for improving performance, energy, and reliability and provide a\r\nreview of interconnect reliability considerations. Finally, we provide a case study to evaluate the efficiency of error correcting codes\r\non a state-of-the-art energy-efficient low-swing interconnect....
A configuration for realizing low input and high output impedances current-mode multifunction filters using multiple output\r\nsecond-generation current conveyors (MOCCIIs) is presented. From the proposed circuit configuration, first-order allpass,\r\nhighpass, lowpass and second-order allpass, notch, bandpass filters can be obtained. The simulation results confirm the theoretical\r\nanalysis....
This paper presents the design of an MMIC oscillator operating at a 38 GHz frequency. This circuit was fabricated by the IIIââ?¬â??V\r\nLab with the new InP/GaAsSb Double Heterojunction Bipolar Transistor (DHBT) submicronic technology (We = 700 nm). The\r\ntransistor used in the circuit has a 15 Ã?µm long two-finger emitter. This paper describes the complete nonlinear modeling of this\r\nDHBT, including the cyclostationary modeling of its low frequency (LF) noise sources. The specific interest of the methodology\r\nused to design this oscillator resides in being able to choose a nonlinear operating condition of the transistor from an analysis in\r\namplifier mode. The oscillator simulation and measurement results are compared. A 38 GHz oscillation frequency with 8.6 dBm\r\noutput power and a phase noise of -80 dBc/Hz at 100 KHz offset from carrier have been measured....
The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or\r\nthousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on\r\nthe chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection\r\nbackbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture\r\nbecomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a\r\npromising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip\r\ncommunications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal\r\nwell with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC.\r\nFinally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed\r\nto break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs....
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